Every Wire Has a Length

"Bandwidth is channels times rate. Channels are pins. Pins are the edge of a package and the length of a trace, and at ten gigabits a second per pin there is almost no length to spare."

The Fit That Reproduces Apple's Numbers

Apple publishes a bandwidth for every chip and never a channel count. The code block infers the count from the memory's transfer rate: a 64-bit LPDDR channel at 6,400 MT/s carries 51.2 GB/s, and two of them are 102 — the M3's "100"; eight are 410, the M3 Max's "400"; sixteen are 819, the M3 Ultra's exact figure. LPDDR5X at 9,600 MT/s makes the M5 ladder the same way: two channels 154, four 307, eight 614, sixteen 1,229 — Apple's "1.2TB/s". Every stated number falls out of one rate and a channel count of two, four, eight or sixteen, and the count doubles with the tier. So the M5 Ultra's bus is 1,024 bits wide: sixteen channels, on four dies (Apple fuses two dual-die M5 Max chips), sixteen packages of memory around them. To double it on the same LPDDR would take thirty-two channels — 2,048 bits, twice the package edge, or eight dies where there are four — or a faster pin, which is LPDDR6's roadmap and not a switch Apple can flip.

Why the Wires Are Short and Soldered

The OEM that built the first serious copy of the pool said why in public: "fanning out that giant 256-bit memory bus requires the LPDDR5x to be soldered", and a socketed layout was "not possible without massively downclocking the memory". That was 256 bits at 8,000 MT/s. JEDEC's own server module standard, SOCAMM2, states its top rate as "up to 9.6Gb/s per pin where platform signal integrity allows" — the qualifying clause is the physics. A signal at that rate on a trace of a few centimetres is a radio-frequency problem: crosstalk between neighbouring wires and simultaneous-switching noise, which a memory vendor's engineers described as "the two dominating factors limiting the achievable data rate" as long ago as the LPDDR2 era, and which get worse with every extra wire switching at once. Apple's bus is 1,024 wires switching at once, at 9,600 MT/s, on a package a few centimetres across. It is soldered because a connector is a length and an impedance discontinuity the signal cannot afford, and it is 1,024 wide because that is what fits around the dies of one Ultra package — two on the M3, four on the M5.

What This Costs Apple, and Everyone

The consequence is the memory track's trade in its hardest form. Wider means more edge: more dies to put memory around, which is how the Ultra gets sixteen channels to the Max's eight — the dies are the edge. Faster means a new generation of memory: LPDDR6 samples at 10.7 Gbps and changes the channel geometry to 24-bit sub-channels, which the density lesson takes up, on the memory vendors' timetable. Neither is a knob. The rivals track showed every copy at a quarter of Apple's width — AMD, NVIDIA, Qualcomm all at 256 bits or less — because 256 is what one die's edge affords with a conventional package, and Apple's advantage is a package that carries four times as many wires without a connector anywhere. The homework, then, is not to want a wider bus but to know that the next one is either more dies, a new memory generation, or a tier — and the two-tier lesson is the one Apple has not shipped on a Mac.

Code

wire_length.py — channels × rate reproduces every Apple figure; what a wider bus would need·python

#!/usr/bin/env python3
"""Every wire has a length. Bandwidth is channels x rate; channels are pins; pins are
package edge and trace length. The physics cross-check that reproduces Apple's figures,
then what a 2x bus would need. Apple publishes bandwidth, not channel counts -- the
channel counts are this quest's inference from the fit."""
per_channel = lambda mts: mts * 8 / 1000            # GB/s per 64-bit channel
apple = [  # chip, MT/s, channels inferred, stated GB/s
    ("M3",       6400,  2,  100), ("M3 Max", 6400,  8, 400), ("M3 Ultra", 6400, 16, 819),
    ("M4",       7500,  2,  120), ("M4 Pro", 8533,  4, 273), ("M4 Max",   8533,  8, 546),
    ("M5",       9600,  2,  153), ("M5 Pro", 9600,  4, 307), ("M5 Max",   9600,  8, 614), ("M5 Ultra", 9600, 16, 1229),
]
print(f"{'chip':9} {'MT/s':>5} {'ch':>3} {'bits':>5} {'fit GB/s':>8} {'stated':>7}")
for chip, mts, ch, stated in apple:
    print(f"{chip:9} {mts:5d} {ch:3d} {ch*64:5d} {per_channel(mts)*ch:8.0f} {stated:7d}")
print("\nto double the M5 Ultra's bandwidth on the same LPDDR: 32 channels = 2,048 bits = twice the package edge, or eight dies where there are four;")
print("or a faster pin: LPDDR6 samples at 10.7 Gbps and its x24 sub-channels change the count -- a roadmap, not a switch.")
print("the OEM that tried a 256-bit socketed bus found it 'not possible without massively downclocking the memory' (Framework, 2025); 1,024 bits is soldered by necessity, not choice.")

Exercise

Run wire_length.py and add any chip whose bandwidth and memory rate you can find — a phone, a console, a laptop. Infer its channel count. Write on your card the widest bus you found outside Apple and the number of dies it sits on, and whether its memory is soldered.

Hint

Consoles and phones are the interesting rows: a games console with GDDR on a 256- or 320-bit bus is a wide bus on one die with soldered chips, which is the same physics reached from the other end. If you find a socketed bus wider than 128 bits at LPDDR rates, check the rate — it will be the downclock the OEM described.