Modularity Moves Inside the Package

"The seam did not disappear. It moved to where only the factory can reach it."

The Industry Went Modular at the Die

While the argument about slots and sockets was going on, the chip industry quietly conceded the modular point one level down. A single huge die is expensive to manufacture — yield falls as area grows — and different parts of a processor want different manufacturing processes. So the industry split processors into chiplets: AMD has built its desktop and server parts from compute dies around an I/O die since 2019; Intel moved its client processors to tiles stacked on its Foveros packaging in 2023; and the UCIe consortium exists so that, eventually, a chiplet from one vendor can sit beside a chiplet from another on a common interface. Apple's version is UltraFusion (2022) and, since March 2026, the Fusion Architecture that makes even the M5 Pro and Max two-die parts.

So at the die level, the whole industry — Apple included — is now modular. What changed is where the interface is. A PCIe slot is on the board, reachable with a screwdriver. A die-to-die link is inside the package, under the lid, reachable by nobody once the part is soldered. The modular good of substitution is still exercised, but by the manufacturer choosing which dies to bond, not by the owner choosing which card to buy.

Why the Package Is Where the Bandwidth Is

The reason the seam moved inside is physics, and it is the same physics as lesson three in reverse. An interface's bandwidth is pins times signalling rate, and pins are cheap when the two sides are millimetres apart on a silicon interposer and expensive when they are centimetres apart on a board. Apple's numbers make the point: UltraFusion joins two M3 Max dies "across more than 10,000 signals, providing over 2.5TB/s"; on the M5 Ultra it is "over 4.4TB/s". NVIDIA's NVLink-C2C, the die-to-die link in its Grace Hopper and Grace Blackwell superchips, is "900 gigabytes per second (GB/s) of coherent interface". A PCIe 5.0 x16 slot is 63 GB/s each way. A Thunderbolt 5 cable is 10. The closer the boundary, the wider it can be — by two orders of magnitude between the interposer and the cable.

Link	Distance	Bandwidth	Who can substitute across it	Evidence
UltraFusion (M5 Ultra)	die to die, interposer	"over 4.4TB/s"	Apple, at manufacture	vendor (Apple, 2026-08-25)
UltraFusion (M3 Ultra)	die to die, interposer	"over 2.5TB/s"	Apple, at manufacture	vendor (Apple, 2025-03-05)
NVLink-C2C (GH200 / GB200)	die to die, superchip	900 GB/s	NVIDIA, at manufacture	vendor (NVIDIA)
Unified memory bus (M3 Ultra)	package	819 GB/s	nobody after purchase	vendor (Apple)
PCIe 5.0 x16	board slot	~63 GB/s per direction	the owner, any vendor	physics (PCI-SIG rate)
Thunderbolt 5	cable	80 Gb/s = 10 GB/s	the owner, any vendor	vendor (Intel, 2023-09-12)

What This Does to the Argument

It sharpens it. The founder's objection to a sealed package is not answered by "but the Ultra is really two chips" — that is modularity for Apple, not for him. And the modular industry's answer is not "put the memory back in a socket" — the socket is exactly the interface whose bandwidth cannot keep up, which is why AMD solders the Ryzen AI Max's memory too. The honest shape of the disagreement in 2026 is this: everyone agrees the seams belong inside the package for performance; the question is who owns the package. A world of UCIe chiplets and CXL memory pools keeps the seams inside and the ownership distributed. Apple's world keeps the seams inside and the ownership with Apple. The convergence track measures how far the first world has actually got.

Code

seams.py — bandwidth falls with distance; substitution rises with it·python

#!/usr/bin/env python3
"""Vendor and physics figures for the boundaries in a modern machine, ordered
by how far apart the two sides are. GB/s; directional where the vendor says so."""

LINKS = [
    # name,                     distance,            GB/s,  who substitutes across it,   evidence
    ("UltraFusion, M5 Ultra",   "die-die interposer", 4400, "manufacturer",              "vendor: 'over 4.4TB/s'"),
    ("UltraFusion, M3 Ultra",   "die-die interposer", 2500, "manufacturer",              "vendor: 'over 2.5TB/s'"),
    ("NVLink-C2C, GH200/GB200", "die-die superchip",   900, "manufacturer",              "vendor: 900 GB/s coherent interface"),
    ("unified memory, M3 Ultra", "package",            819, "nobody after purchase",     "vendor"),
    ("PCIe 5.0 x16",            "board slot",           63, "owner, any vendor",         "physics from 32 GT/s"),
    ("Thunderbolt 5",           "cable",                10, "owner, any vendor",         "vendor: 80 Gb/s"),
]

print(f"{'link':26} {'distance':20} {'GB/s':>6}  substitution by")
for name, dist, gbs, who, _ in LINKS:
    print(f"{name:26} {dist:20} {gbs:6d}  {who}")

top, bottom = LINKS[0][2], LINKS[-1][2]
print(f"\ninterposer / cable = {top / bottom:.0f}x   (the price of a boundary you can unplug)")

Exercise

Run seams.py and add a row for the last interface you personally replaced a part across (a DIMM slot, an M.2 slot, a PCIe slot, a USB port), with its bandwidth from the standard's spec. Then answer: at which row does the substitution column change hands from the manufacturer to the owner, and what is the ratio of bandwidths across that one line? That ratio is the number this whole track is about.

Hint

The line falls between the package and the board slot: 819 GB/s (unified memory, nobody) to 63 GB/s (PCIe, anyone). About 13x. Everything above the line is Apple's — or AMD's, or NVIDIA's — decision at manufacture; everything below it is yours.