An Industry Built on Interfaces

"A standard is a boundary two strangers agreed to meet at."

What an Interface Actually Specifies

An interface, in the sense this track means, is a contract with three parts. Mechanical: the physical shape — a slot's dimensions, a socket's pin grid, a connector's keying — so that a part fits. Electrical: voltages, timings, signal integrity budgets, so that a part that fits also works. Protocol: what the signals mean — a memory command, a PCIe transaction, a USB packet — so that two parts that work together also understand each other. Publish all three and anyone can build either side. Withhold any one and you have a proprietary connector.

The PC industry's interfaces are governed by bodies whose entire job is publishing those contracts:

Boundary	Interface	Who publishes it	What substitution it enables
processor ↔ software	x86-64 instruction set	Intel and AMD, de facto	two processor vendors run the same binaries
processor ↔ memory	DDR5 / LPDDR5X, DIMM, CAMM2, SOCAMM2	JEDEC	any memory vendor's module in any board's slot
processor ↔ expansion	PCI Express (5.0, 6.0)	PCI-SIG	any GPU, NIC or SSD in any slot
machine ↔ peripherals	USB, Thunderbolt, DisplayPort	USB-IF, Intel/USB-IF, VESA	any device on any machine
die ↔ die (new)	UCIe	UCIe Consortium (formed March 2022)	chiplets from different vendors in one package
processor ↔ pooled memory (new)	CXL 2.0 / 3.0	CXL Consortium	memory pooled and shared across hosts over a switch

The Newest Boundaries Are Inside the Package

The bottom two rows are the ones that matter for this quest, because they are where the modular industry is answering Apple. UCIe — Universal Chiplet Interconnect Express — exists to do for dies what PCIe did for cards: its own description is "defining the interconnect between chiplets within a package", and the consortium that formed in March 2022 to write it includes AMD, Arm, Intel, Qualcomm, Samsung, TSMC, Google Cloud, Meta and Microsoft. The 3.0 specification was published in August 2025. Apple is not on the founding list; UltraFusion is Apple's private answer to the same problem, announced the same week (M1 Ultra on 2022-03-08, six days after UCIe's founding), and unpublished.

CXL — Compute Express Link — is the interface that attacks the other half of Apple's package: memory. CXL 2.0 (2020) "allows for pooling through the use of switches", so that a rack's memory can be lent to whichever host needs it; CXL 3.0 adds "the concept of memory sharing", where several hosts see the same bytes. This is the modular industry's route to large memory without soldering it to one processor, and it is the answer to "why not just do what Apple did" that the convergence track returns to.

Substitution Is the Point; Everything Else Is the Price

Look at the fourth column of the table. Every row is a place where a buyer can walk away from one vendor and toward another without changing anything else in the machine. That is the economic content of an interface, and it is worth being clear-eyed about what it has bought: forty years of price competition in memory, storage, graphics and processors, and a repair culture in which a dead part is a part. Apple silicon keeps the rows at the edges of the machine — USB, Thunderbolt, DisplayPort — and deletes the rows in the middle. The next lesson prices that deletion in physics; this one just wanted you to see how many rows there were.

Code

contract.py — an interface is three published parts, or it is a proprietary connector·python

#!/usr/bin/env python3
"""Mechanical + electrical + protocol, all published = an interface two
strangers can meet at. Anything less is a connector one vendor owns."""
from dataclasses import dataclass


@dataclass(frozen=True)
class Contract:
    name: str
    mechanical: bool     # published shape / pinout
    electrical: bool     # published voltages, timings, budgets
    protocol: bool       # published meaning of the signals
    publisher: str

    @property
    def open_interface(self) -> bool:
        return self.mechanical and self.electrical and self.protocol


CONTRACTS = [
    Contract("PCI Express 5.0",  True,  True,  True,  "PCI-SIG"),
    Contract("DDR5 DIMM",        True,  True,  True,  "JEDEC"),
    Contract("USB4",             True,  True,  True,  "USB-IF"),
    Contract("UCIe 3.0",         True,  True,  True,  "UCIe Consortium"),
    Contract("CXL 3.0",          True,  True,  True,  "CXL Consortium"),
    Contract("UltraFusion",      False, False, False, "Apple (undisclosed)"),
    Contract("Apple on-package LPDDR5", False, False, True, "JEDEC protocol, Apple packaging"),
]

for c in CONTRACTS:
    kind = "open interface  " if c.open_interface else "vendor boundary "
    print(f"{kind} {c.name:26} {c.publisher}")

Exercise

Run contract.py, then add three rows for interfaces you actually use — a display connection, a storage connection, and one you think might be proprietary. For the proprietary one, say which of the three parts is missing and who could publish it if they chose to. Then write one sentence on what an owner would gain if Apple published UltraFusion's contract, and one on why that gain would still not reach the owner.

Hint

Publishing UltraFusion would let another company design a die that sits beside an M-series die in a package Apple manufactures. It would not put a socket in your Mac Studio. Modularity inside the package is a manufacturer's good; the owner sees it only as a price.