"The first serious copy is a 256-bit bus on one die with 128 gigabytes soldered to it. Read it as an M-series Ultra with a quarter of the pins — a Max with half — and its numbers stop being surprising."
Strix Halo, in the Vendor's Words
AMD's Ryzen AI Max+ 395 — the part the press calls Strix Halo — is the first x86 chip built at the M1 Max's scale — a CPU, a large integrated GPU and an NPU on one package, sharing one 128 GB pool over a 256-bit bus (Intel's Lunar Lake, the next lesson, copied the M1's diagram a year earlier at laptop size). AMD's specification page lists "256-bit LPDDR5x", "Max. Memory 128 GB", "LPDDR5x-8000", an NPU of "Up to 50 TOPS", and a "Default TDP 55W" configurable to 120. The bandwidth follows from the first three numbers: 256 bits × 8,000 MT/s ÷ 8 is 256 GB/s, which is what AMD says it "doubles the bandwidth to". That is a shade under an M4 Pro's 273 (the same 256-bit bus, on LPDDR5X-8533), under two-thirds of an M3 Max's 400 and under a third of an M3 Ultra's 819 — and those two run LPDDR5-6400, slower pins than AMD's. Against the big Macs the difference is the bus, 256 bits against the Max's 512 and the Ultra's 1,024, not the memory technology; against the M4 Pro there is no difference to speak of. The bus width is the story of this track.
Why It Is Soldered, in the OEM's Words
The Framework Desktop, the first small computer built on the chip, was announced with an unusual explanation. Its founder, reporting what AMD's engineers told him: "fanning out that giant 256-bit memory bus requires the LPDDR5x to be soldered"; a socketed layout was "not possible without massively downclocking the memory". That is the memory track's argument from the other side of the industry. The first company to put memory on a module in a modular PC tried to keep it modular and could not, because signal integrity on a 256-bit bus at 8,000 MT/s does not survive a connector — and Apple's bus is twice as wide on the Max, four times on the Ultra. The pool's shape forces the package's shape; AMD arrived at Apple's conclusion by the same physics, and said so through its partner.
What the Pool Can Address, and the Successor
On Windows, AMD's "Variable Graphics Memory" lets the user "reallocate a % of the system RAM to integrated graphics", up to "96GB VGM" for a "total graphics memory size of 112GB"; on Linux, AMD's developers describe raising the allocator's limit to "120GB per node". Those are the GPU track's claimant-discipline knobs, exposed as settings instead of an OS recommendation — the same problem the Mac's recommended working set solves, solved by hand. The 2026 refresh the press calls Gorgon Halo lifts the ceiling to 192 GB with up to 160 GB addressable as VRAM and the same bus, and AMD describes its flagship as the first x86 client part able to run a 300-billion-parameter model locally — at 256 GB/s, a ceiling the physics track can compute in a line: a 300B at the lab's 4.7 bits per weight is about 175 GB per token if dense, so about 1.5 tokens a second; a mixture reads far less and runs far faster, which is the experts lesson and the reason the marketing sentence chose a mixture. The copy is real, honest about its physics, and a quarter of the Ultra's width; the next lesson is the vendor that tried and stepped back.