Intel's One-Off

"Intel built the M1's shape once, shipped it, and told its shareholders it would not do it again. The reason was not physics. Read the reason; it is the modular track's referee speaking in dollars."

Lunar Lake, the Copy

In September 2024 Intel launched the Core Ultra 200V family, code-named Lunar Lake, and its own fact sheet listed the feature this quest is about in Apple's words: "Memory on Package – Enables fast access to data and reduces latency, decreasing the overall power consumption of the system"; "Up to 32GB 2ch memory / Memory on package / LPDDR5x-8533". A laptop chip with the DRAM in the package, on a 128-bit bus at the fastest rate LPDDR5X then ran — the M1's diagram, four years later, at the M1's bus width and twice its rate. The bandwidth follows, about 137 GB/s, and so does the ceiling: 32 GB, the largest pool Intel would sell — a 27B at 4 bits with almost nothing to spare, a 9B comfortably — and the physics track's whole argument in one number.

The Retreat, in the CEO's Words

Six weeks later, on the third-quarter earnings call, an analyst asked why memory needed to be in the package and whether it would continue. The chief executive's answer, from the transcript: "it really is, for us, a one-off with Lunar Lake. That will not be the case with Panther Lake, Nova Lake and its successors as well. We'll build it in a more traditional way with memory off-package and the CPU, GPU, NPU and I/O capabilities in the package. But volume memory will be off-package in the road map going forward." The chief financial officer had just said why: the arrangement was "having a pretty meaningful impact, a significant impact on Lunar Lake's gross margins" — because when the chip vendor buys the DRAM and sells it inside the package, the memory vendor's dollars pass through the chip vendor's books at the chip vendor's margin, and the PC industry's convention is that the system builder buys memory. The successor, Panther Lake, supports DDR5 on SO-DIMM modules: off the package, on a socket, at a lower rate.

What the One-Off Proves

The convergence has a counter-example, and it is instructive because the reason is not the physics. Nothing Intel said disputes that memory on the package is faster, lower-latency and lower-power — its own fact sheet claims all three. What it disputes is who should own the DRAM on the invoice. Apple sells the whole computer and books the memory at the computer's margin; Intel sells a chip into a horizontal industry where the memory is someone else's line item, and putting it in the package moved a low-margin commodity onto a high-margin chip's ledger. That is the modular track's Grove-and-Christensen structure exactly: the horizontal industry's layers each defend their margin, and an integrated design that crosses a layer boundary pays for it in the crossing's accounting even when it wins on the bench. The pool's physics is copyable by anyone; the pool's business model is copyable only by a company that sells the box. Which is why AMD's copy ships in machines from a small OEM at a price near a Mac's, and why the largest x86 vendor built it once and went back.

Code

intel_one_off.py — on package and off, as bus width, rate and ceiling·python

#!/usr/bin/env python3
"""Intel's one-off, as arithmetic: what memory on the package bought Lunar Lake, and what
its successor gave back by moving memory off the package. Vendor figures; the bandwidth
column is width x rate / 8."""
parts = [  # name, memory placement, bus bits, MT/s, max GB, source
    ("Intel Core Ultra 200V (Lunar Lake, 2024)", "on package",  128, 8533, 32,  "Intel fact sheet: 'Memory on Package', LPDDR5x-8533, up to 32GB"),
    ("Intel Panther Lake (2026)",                "off package", 128, 7200, None, "Intel comparison PDF: DDR5-7200 SO-DIMM (capacity is the module's, not the chip's)"),
    ("Apple M1 (2020)",                          "on package",  128, 4266, 16,  "Apple: 'a single pool within a custom package'"),
    ("Apple M3 Ultra (2025)",                    "on package", 1024, 6400, 512, "Apple: 819GB/s, up to 512GB"),
]
print(f"{'part':44} {'memory':12} {'bus':>4} {'MT/s':>5} {'GB/s':>5} {'max GB':>6}")
for name, place, bits, mts, gb, src in parts:
    print(f"{name:44} {place:12} {bits:4d} {mts:5d} {bits*mts/8/1000:5.0f} {(str(gb) if gb else 'module'):>6}")
print()
print("Lunar Lake's package bought signal integrity for 8,533 MT/s on a laptop board and a 32 GB ceiling;")
print("Panther Lake's SO-DIMM gives up the rate for the ceiling and the socket -- the modular track's trade, chosen for margin.")

# part                                         memory        bus  MT/s  GB/s max GB
# Intel Core Ultra 200V (Lunar Lake, 2024)     on package    128  8533   137     32
# Intel Panther Lake (2026)                    off package   128  7200   115 module
# Apple M1 (2020)                              on package    128  4266    68     16
# Apple M3 Ultra (2025)                        on package   1024  6400   819    512

Exercise

Find the current memory placement of one x86 laptop chip you can name — on package or on a module — and its maximum memory and rate. Add it to intel_one_off.py. Then write on your card, in one sentence, whether the vendor's choice was a physics choice or a margin choice, citing what the vendor itself said.

Hint

If the vendor's own material praises on-package memory and the product ships with sockets anyway, the reason is the invoice; if it ships on-package with a hard ceiling, the reason is the fan-out. Both are honest, and the card should name which.