"The edge went integrated; the data centre is going modular again — pooled, shared, replaceable. Both are right, because the referee's line runs between them."
Memory Comes Off the Package Again
Every lesson in this track watched memory move onto the package. At server scale it is moving off. NVIDIA's Vera CPU pairs LPDDR5X with "SOCAMM, detachable, field-replaceable modules" for "up to 1.5 TB of memory" at "up to 1.2 terabytes per second"; Micron has its 192 GB SOCAMM2 in high-volume production and a 256 GB part announced, and Samsung describes the form factor as enabling "easy memory upgrades or replacements without any mainboard modification". The rate the module gives up is small and stated: JEDEC's SOCAMM2 reaches "up to 9.6Gb/s per pin where platform signal integrity allows", against the 10.7 Gbps SK hynix samples for soldered LPDDR6, while the laptop-class LPCAMM2 ships at 8,533 MT/s and Micron notes it "requires a new type of socket, which also adds cost". The code block ranks them: every module is a step down the per-pin rate for a step up in replaceability, and a server with a terabyte and a half of it can afford the step. A 1,024-bit bus on a Studio cannot — the OEM lesson's fan-out is the reason — and that is the line: modular memory wins where capacity is measured in terabytes and the bus is spread across a board, integrated memory wins where the bus is wide and the board is a laptop.
Pooling, Sharing, Chiplets
Two standards push modularity into the memory itself. CXL, over PCIe-class links, "allows for pooling" in version 2.0 — memory in a box that several hosts draw on — and in 3.0 "in addition to memory pooling, we introduce the concept of memory sharing": one region, many hosts, at fabric latency. That is the interface lesson's price paid on purpose, because the thing bought is a memory that belongs to no single machine. UCIe standardizes "the interconnect between chiplets within a package", so the package itself becomes modular — dies from different vendors behind one link, a consortium formed in 2022 by Intel, AMD, Arm, Qualcomm, Samsung, TSMC and the cloud companies. Apple's UltraFusion is the proprietary version of the same idea, two dies as one chip; the difference is who is allowed to supply the second die. Both standards say the same thing as the referee: once a boundary's performance is good enough, the industry standardizes the boundary and competes across it.
Throughput, the Half the Pool Never Wins
The last place modular strikes back is not a standard but a workload. The physics track's batch lesson measured the Mac serving 32 streams at seven times its single-stream rate; the rival track priced why a card does better — batch turns decode into compute, and tensor cores win compute fifty to one. A rack of cards with HBM behind NVLink, serving thousands of users, is the modular world at its best: small fast memories, wide links, work spread across them, memory pooled over CXL for the parts that do not need to be fast. The pool wins the single stream on a model that does not fit a card; the rack wins every stream at once on the models that do. The household is a single stream in a room, which is why its fleet is Macs — and it uses the cloud, on the rack's side of the line, for the voices and the frontier models where quality wins, which is the fleet track's cloud-by-choice lesson. Modular did not lose to unified. The line between them moved, and this quest has spent eleven tracks locating it.