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Lesson 04 of 05 · published

What Copying Proves, and What It Doesn't

~13 min · convergence, christensen, modularity, bus-width, software-moat, our-judgment

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"Being copied is the market's way of saying the shape was right. It is also the market's way of saying the shape is no longer yours. Both sentences are true, and the referee decides which one matters this year."

The Shape Was Right

Three lessons of evidence: AMD built the pool and its OEM explained the soldering with Apple's physics; Intel built it, praised it in its own fact sheet, and retreated for margin; Qualcomm built it twice and NVIDIA, per the press, is bringing it to Windows with CUDA attached; NVIDIA already sells it in the DGX Spark and at rack scale. When every vendor of PC silicon converges on one diagram within six years, the diagram is not a preference. It is what the wall's other side looks like when the workload is a model that must be read whole per token — the physics track's formula, drawn as a package. The mouse track argued that Apple built the shape for video and found the model by accident; the copies prove the accident generalizes, because none of the copiers were building for ProRes.

The Lead Is Narrower Than It Looks, and Wider

The code block measures the lead the only way a spec sheet allows: bus width by year. The M1's 128-bit pool was matched by a PC chip in 2024, four years later. Nothing outside Apple has shipped a 512-bit PC pool — the M1 Max's width from 2021 — and nothing has shipped 1,024 bits, the Ultras' width since 2022. On capacity, the copies reached 128 GB in 2025 and 192 in 2026; the Ultras have sold 512 since 2025. So the copies are four to five years behind on width and about two behind on capacity, and the two numbers together — bandwidth per gigabyte, the pool's law from the rival track — put every copy on the Mac's curve, the widest at a quarter of the Ultra's width and the rest narrower. That is the narrow reading. The wide reading is the mouse track's: the width is copyable, given the package engineering the homework track prices, and the software path is what took five years — llama.cpp on Metal, MLX, the Ollama engine, a community that learned the Mac's quirks — and that is not on the spec sheet, and a copier with CUDA does not need to build it.

The Referee's Ruling

The modular track's referee, in Christensen's words: "Integration provides advantages whenever a product is not good enough to meet customer needs"; once it is more than good enough, "competition forces firms to compete on convenience or customization" — and the Institute's sentence about Apple's own history: "Apple's proprietary architecture, which in the not-good-enough circumstance was a strength, became a disadvantage in the more-than-good-enough circumstance." Apply it to the pool. For models that fit 128 GB and decode acceptably at 256 GB/s — the household's 9B, most people's daily models — the copies are good enough, and the referee says convenience and software will decide: CUDA, Windows, price, the OEM you already buy from. Apple's exclusivity is weaker there every year, and this quest says so. For models above 128 GB, or a household that wants a 27B at more than 18 tokens per second in a silent box, nothing else is good enough yet, and integration's advantage stands at four to five years of bus width. The line between the two moves toward Apple's numbers each year the copies widen their buses; it moves away each year Apple widens its own. Direction is not timing; the last track is about that.

Code

width_lag.py — Apple's pool widths by year against the widest copy, and the lag·python
#!/usr/bin/env python3
"""What copying proves, as a table of bus widths by year. Apple's pools on the left,
the widest non-Apple PC pool shipped that year on the right. Vendor figures; the lag
is the first year a copy matched each Apple width, or '-' if none has."""
apple = [(2020, "M1", 128, 16), (2021, "M1 Max", 512, 64), (2022, "M1 Ultra", 1024, 128),
         (2023, "M2 Ultra", 1024, 192), (2024, "M4 Max", 512, 128), (2025, "M3 Ultra", 1024, 512), (2026, "M5 Ultra", 1024, 512)]
copies = [(2024, "Intel Lunar Lake", 128, 32), (2024, "Qualcomm X Elite", 128, 64),
          (2025, "AMD Strix Halo", 256, 128), (2025, "NVIDIA GB10", 256, 128),
          (2026, "Qualcomm X2 Elite Extreme", 192, 128), (2026, "AMD Gorgon Halo", 256, 192),
          (2026, "NVIDIA RTX Spark (press)", 256, 128)]
print(f"{'year':>4}  {'Apple pool':10} {'bus':>5} {'GB':>4}   |  {'widest copy that year':28} {'bus':>5} {'GB':>4}")
by_year = {}
for y, n, b, g in copies:
    if y not in by_year or b > by_year[y][1]: by_year[y] = (n, b, g)
for y, n, b, g in apple:
    c = by_year.get(y)
    print(f"{y:4d}  {n:10} {b:5d} {g:4d}   |  " + (f"{c[0]:28} {c[1]:5d} {c[2]:4d}" if c else f"{'—':28}"))
print()
for y, n, b, g in apple:
    first = next((cy for cy, cn, cb, cg in sorted(copies) if cb >= b), None)
    print(f"{n:10} {b:4d}-bit, {g:3d} GB ({y}): first non-Apple PC pool at this width " + (f"{first} — {first - y} years later" if first else "— none yet"))

# year  Apple pool   bus   GB   |  widest copy that year          bus   GB
# 2020  M1           128   16   |  -
# 2021  M1 Max       512   64   |  -
# 2022  M1 Ultra    1024  128   |  -
# 2023  M2 Ultra    1024  192   |  -
# 2024  M4 Max       512  128   |  Intel Lunar Lake               128   32
# 2025  M3 Ultra    1024  512   |  AMD Strix Halo                 256  128
# 2026  M5 Ultra    1024  512   |  AMD Gorgon Halo                256  192
# M1 128-bit (2020): first non-Apple PC pool at this width 2024 - 4 years later; 512-bit and 1024-bit: none yet

External links

Exercise

Run width_lag.py and add the next copy you hear about, with its bus width and capacity. Then write on your card which side of the referee's line your own models sit on — good enough on a 128 GB, 256 GB/s pool, or not — and therefore whether, for you, the copies matter this year.
Hint
If your largest model is under 60 GB and you accept 15–20 tokens per second, you are on the commodity side and software and price decide; if not, you are on the Mac's side until a copier ships a 512-bit bus. Write the year you expect that, and check it next year.

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