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Lesson 03 of 06 · published

Six Generations, Named Honestly

~15 min · map, generations, process-node, m5, vendor-claims

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"A generation number tells you when. It does not tell you how much."

The Ladder by Year

GenerationFirst shippedProcess (Apple's words)Base-chip bandwidthTop-tier bandwidthEvidence
M12020-115 nmnot published (~68 GB/s by our fit)M1 Ultra 800 GB/s (2022-03)vendor + physics
M22022-06second-generation 5 nm100 GB/sM2 Ultra 800 GB/s (2023-06)vendor
M32023-103 nm100 GB/sM3 Ultra 819 GB/s (2025-03)vendor
M42024-05second-generation 3 nm120 GB/sM4 Max 546 GB/s (no Ultra)vendor
M52025-10third-generation 3 nm153 GB/sM5 Ultra "1.2TB/s" (announced 2026-08-25, ships 2026-09-22)vendor
M6announced 2026-08-252 nm — "Apple's first state-of-the-art 2-nanometer chip"not publishedvendor (announcement only)

Two honest readings of that table. First, the base chip's bandwidth roughly doubled across five generations (68 → 153 GB/s) while the top tier grew by about half (800 → 1,229 GB/s). The dramatic numbers in Apple silicon come from tiers, not from generations: an M1 Ultra from 2022 still out-feeds an M5 Max from 2026. Second, the memory technology drove the generation gains: LPDDR4X to LPDDR5 (M1→M2), then LPDDR5X at 7500, 8533 and 9600 MT/s (M4, M4 Pro/Max, M5). The process node shrank once in the same period (5 nm to 3 nm at M3) and then went through two revisions of 3 nm, and none of it moved the bandwidth number, because bandwidth lives in the memory and the bus, not in the transistors.

What Changed Shape in the M5 Generation

Two things, both vendor-described and neither measured in this quest. The M5 Pro and M5 Max are built from two third-generation 3 nm dies — Apple calls it the Fusion Architecture and says it "connects two dies into a single SoC" using advanced packaging; the per-die contents are not disclosed. The M5 Ultra then joins two of those dual-die Max chips with UltraFusion into "the quad-die architecture — a first for Apple silicon", with inter-die bandwidth "over 4.4TB/s". So the die count per tier went 1/1/1/2 (M3 family) to 1/2/2/4 (M5 family). Keep that in mind for the next lesson, where "monolithic" gets three meanings.

The M5 generation also introduced per-core Neural Accelerators in the GPU and a new core naming — "super cores" plus "performance cores", with no efficiency cores listed for Pro, Max and Ultra. The CPU track covers what that means; here it is enough to note that Apple's own M5 numbers attribute prefill gains to the accelerators and decode gains to bandwidth, which is exactly the split this quest is built around.

Vendor Claims, With Their Baselines

ClaimStage it measuresBaselineSource
M5: "over 4x the peak GPU compute performance compared to M4"peak metric, not a workloadM4Apple newsroom, 2025-10-15
M5 Pro/Max: "up to 4x faster LLM prompt processing than M4 Pro and M4 Max"prefillM4 Pro / M4 MaxApple newsroom, 2026-03-03
M5 Ultra: "up to 4.3x the peak AI compute performance when compared to M3 Ultra"peak metricM3 Ultra 32C/80G 512 GB, tested July 2026Mac Studio release, 2026-08-25
M5 Ultra: "up to 4.5x the peak GPU compute for AI compared to M3 Ultra"peak metricM3 Ultra 32C/80G 256 GB, tested August 2026M6/M5 Ultra release, same day
M5 Ultra: "up to 4x faster [LLM prompt processing] than M3 Ultra" in LM StudioprefillM3 UltraMac Studio release, 2026-08-25

Notice the two same-day releases disagree — 4.3x against 4.5x for what reads as the same comparison, with different baseline configurations and test months in the footnotes. That is not a scandal; it is what "peak" means. It is also why this quest never copies a vendor multiplier without the stage and the baseline beside it, and why the M5 generation appears here as claims only: the household's newest Mac Studio is an M3 Ultra, and no M5 number in this quest is measured. When an M5 Ultra is measured, that is an evolve, not a guess.

Code

generations.py — bandwidth growth by generation vs by tier·python
#!/usr/bin/env python3
"""Where did the bandwidth come from: the generation number, or the tier?
Vendor GB/s except M1 base, which Apple never published (fit: LPDDR4X-4266 × 2)."""

BASE = {"M1": 68.3, "M2": 100, "M3": 100, "M4": 120, "M5": 153}
TOP  = {"M1": 800, "M2": 800, "M3": 819, "M4": 546, "M5": 1229}   # Ultra, or Max where no Ultra
MEM  = {"M1": "LPDDR4X-4266", "M2": "LPDDR5-6400", "M3": "LPDDR5-6400",
        "M4": "LPDDR5X-7500 (base) / 8533 (Pro, Max)", "M5": "LPDDR5X-9600"}

print("generation  base GB/s  top GB/s  top/base   memory technology")
for g in BASE:
    print(f"{g:10}  {BASE[g]:9.1f}  {TOP[g]:8.0f}  {TOP[g]/BASE[g]:8.1f}x  {MEM[g]}")

print(f"\nbase chip, M1 -> M5: {BASE['M5']/BASE['M1']:.2f}x over five generations")
print(f"top tier,  M1 -> M5: {TOP['M5']/TOP['M1']:.2f}x over five generations")
print(f"within M3, base -> Ultra: {TOP['M3']/BASE['M3']:.1f}x in one generation")

External links

Exercise

Take one Apple performance claim about any M-series chip from a source of your choice and rewrite it as a four-column row: the claim verbatim, the stage it measures (prefill, decode, a peak metric, a benchmark app), the baseline configuration named in the footnote, and what you would need to measure yourself to turn it into a decode expectation. If the footnote is missing, say so — that is a finding, not a failure.
Hint
Apple's footnotes name the exact baseline unit and the test month. "Prompt processing" and "time to first token" are prefill; "tokens per second" without a stage is usually decode; "peak compute" is neither — it is a ceiling nothing reaches.

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