Base, Pro, Max, Ultra: What Changes Between Tiers

"The tier names sound like trim levels on a car. They are closer to lane counts on a road."

Four Names, Three Variables

Within one generation, Apple sells the same core designs in four packages. What changes between them is not the speed of any one core — an M3 Max performance core is the same core as the one in a base M3 — but three quantities that scale together: how wide the memory bus is, how many GPU cores sit behind it, and how much memory can be soldered to the package. The CPU core count grows too, but it is the least important of the four for anything in this quest.

The M3 family, from Apple's own spec pages (every cell here is a vendor number, the Evidence column says so):

Chip	CPU	GPU cores	Max memory	Bandwidth	Evidence
M3	4P + 4E	10	24 GB	100 GB/s	vendor (tech specs)
M3 Pro	6P + 6E	18	36 GB	150 GB/s	vendor (tech specs)
M3 Max (16C/40G)	12P + 4E	40	128 GB	400 GB/s	vendor (tech specs)
M3 Ultra (32C/80G)	24P + 8E	80	512 GB at launch	819 GB/s	vendor (tech specs; newsroom says "over 800GB/s")

Read the bandwidth column as a ratio: 1 : 1.5 : 4 : 8. Read the GPU column: 1 : 1.8 : 4 : 8. The two columns track each other because they are the same design decision — a GPU that is four times larger needs four times the memory traffic to stay fed, and the way to get four times the traffic from the same memory technology is four times the channels. The Ultra doubles the Max because it is two Max dies, joined across Apple's UltraFusion interposer, each carrying its own memory channels.

Where the Bandwidth Number Comes From

Bandwidth is not a magic property of a chip. It is transfer rate × bytes per transfer × channels. The M3 family uses LPDDR5 at 6400 MT/s; one 16-bit channel moves 2 bytes per transfer, so a channel pair (32 bits) delivers 6400 × 4 = 25.6 GB/s, and Apple's published figures fit a 64-bit slice at 51.2 GB/s: two slices for the base M3 (102.4, sold as "100"), eight for the Max (409.6, sold as "400"), sixteen for the Ultra (819.2, sold as "819"). The code block does that arithmetic for every chip in the ledger and prints the fit beside the vendor figure. Apple does not publish channel counts; the counts are our inference from the fit, and the lesson labels them that way.

That is the whole tier system in one formula. It is also why a base M3 Ultra with 96 GB and one with 512 GB have identical bandwidth: capacity is how many bits each channel's chips hold; bandwidth is how many channels there are. The memory track returns to this distinction because it decides which Mac can run a model at all (capacity) and how fast it will run it once loaded (bandwidth).

What Does Not Change

The instruction set, the core microarchitecture, the Neural Engine (16 cores in the base, Pro and Max; 32 in the Ultra, because it is two dies), the media engines (the Max and Ultra get extra encoders, but the design is the same), the page size, the operating system's memory rules. A program that runs on an M3 MacBook Air runs unchanged on an M3 Ultra; it simply has more lanes and a bigger pool. This is the property that lets a household run one code path across nine Macs of four generations, and it is the property the lab track exploits: three M3 tiers under one microarchitecture isolate the effect of bandwidth and capacity from everything else.

Code

bandwidth_fit.py — vendor bandwidth explained by transfer rate × channels·python

#!/usr/bin/env python3
"""Bandwidth = MT/s × 8 bytes × 64-bit channels. Apple publishes the GB/s and
the memory generation; the channel counts below are OUR INFERENCE from the fit."""

CHIPS = [
    # chip,        MT/s,  64-bit channels, vendor GB/s
    ("M3",         6400,  2,   100),
    ("M3 Pro",     6400,  3,   150),
    ("M3 Max 40G", 6400,  8,   400),
    ("M3 Ultra",   6400, 16,   819),
    ("M2 Ultra",   6400, 16,   800),
    ("M4 Pro",     8533,  4,   273),
    ("M4 Max 40G", 8533,  8,   546),
    ("M5 Max 40G", 9600,  8,   614),
    ("M5 Ultra",   9600, 16,  1229),   # Apple: "1.2TB/s"
]

print(f"{'chip':12} {'MT/s':>6} {'ch':>3} {'fit GB/s':>9} {'vendor':>7} {'delta':>6}")
for chip, mts, ch, vendor in CHIPS:
    fit = mts * 8 * ch / 1000          # 8 bytes per transfer on a 64-bit channel
    print(f"{chip:12} {mts:6d} {ch:3d} {fit:9.1f} {vendor:7d} {fit - vendor:+6.1f}")

# The point: bandwidth is a lane count. Same memory chips, more channels.

Exercise

Add your Mac's tier, GPU core count and vendor bandwidth to the card from lesson one (the tech-specs page for your model has all three). Then run bandwidth_fit.py and add your chip as a new row: which transfer rate and channel count reproduce the vendor number? If none fits cleanly, say what you would need to know to settle it.

Hint

M1 and M2 base chips use LPDDR4X-4266 and LPDDR5-6400; M4 moved to LPDDR5X-7500 (base) and 8533 (Pro/Max); M5 uses LPDDR5X-9600. If your fit is off by a factor of two, you counted 32-bit channels where the script counts 64-bit ones — both conventions exist, and neither is published by Apple.