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Lesson 03 of 05 · published

Qualcomm and the Arm PC

~13 min · convergence, qualcomm, arm, npu, tops, windows-on-arm, vendor-claim

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"The Arm PC copied the Mac twice: the instruction set, and the pool. Its marketing leads with a third number the Mac's decode never divides by."

The Second Convergence: the Instruction Set

The CPU track told the story of Apple moving the Mac to its own Arm cores in 2020. The Windows PC followed on a longer fuse: Qualcomm's Snapdragon X Elite in 2024 was the first Arm chip sold at scale into Windows laptops with a translation layer for the x86 software the industry had accumulated — Rosetta's problem, four years later, at the other vendor. Its product brief lists LPDDR5x at 8,448 MT/s, "Up to 64 GB", "135 GB/s", and an NPU of "45 TOPS"; that is a 128-bit bus at the M4's class of bandwidth, with the M4's class of ceiling — a 9B at 30 tokens per second, a 27B not worth running. The 2026 X2 Elite raises the memory to 128 GB and the top part, the X2 Elite Extreme, widens the bus to 192 bits for "228 GB/s" and an 80-TOPS NPU; the lower X2 SKUs keep 128 bits at 152. Both are pools; both are the Mac's diagram; both sit at a fraction of the Max's bus width, a step narrower than AMD's 256 bits.

The Number the Marketing Leads With

Every Arm PC launch leads with TOPS — trillions of NPU operations per second — and the number is real, and it is the wrong number for a language model's decode. The Core ML lesson measured why on Apple's own unit: a neural engine is a compute engine with a narrow door to the pool, and decode is a bandwidth stage that reads every weight per token. The X2 Elite Extreme's 80 TOPS decodes a 9B at the same 51 tokens-per-second ceiling that a GPU on the same 228 GB/s would, because the ceiling is bytes over bandwidth and TOPS never appear in it. Sort the code block's table by the bandwidth column and the Arm PCs land between the M4's row and the M4 Pro's (the Extreme's 228 against 120 and 273); sort it by TOPS and they lead the M4's Neural Engine, and the ordering means nothing for the token. Apple's own M4 newsroom line — the Neural Engine "capable of up to 38 trillion operations per second" — is the same kind of claim from the other side, and this quest treats both as vendor metrics for the compute stage, which is where they belong.

The Datum That Changes the Track

The press reports a third Arm PC vendor for 2026: NVIDIA, with a chip the press calls RTX Spark, "the consumer-oriented sibling of the GB10" — an Arm CPU and a Blackwell GPU behind NVLink-C2C with "up to 128GB of unified memory", built for Windows laptops and compact desktops from the major OEMs, reported to be arriving as Qualcomm's exclusive arrangement for Windows on Arm lapses. This quest has measured none of it and labels it press. If it ships as described, it is the strongest datum in the track: the Mac's shape — Arm cores, a large GPU, a 128 GB pool on a 256-bit bus — with the CUDA platform from the rival track attached, sold into the PC market at the same bandwidth point as the DGX Spark. The copy that matters was never a wider LPDDR bus; it is the pool with twenty years of software on it, and it is the reason the next lesson asks what copying proves about the mouse.

Code

arm_pcs.py — the Arm PCs against the Mac, sorted by the number that decodes·python
#!/usr/bin/env python3
"""Qualcomm and the Arm PC: the NPU number the marketing leads with, and the bandwidth
number decode actually divides by. Vendor briefs; RTX Spark from press. Ceilings for
a 9B at 4 bits (4.47 GB/token, the lab's figure) and a 27B (14.42)."""
chips = [  # name, year, GB/s, max GB, NPU TOPS, source
    ("Qualcomm Snapdragon X Elite",          2024, 135, 64,  45, "Qualcomm brief Rev C 2024-04: LPDDR5x 8448 MT/s, 135 GB/s, up to 64 GB, 45 TOPS"),
    ("Qualcomm Snapdragon X2 Elite",         2026, 152, 128, 80, "Qualcomm brief Rev C 2026-01: 128-bit, 152 GB/s, 128 GB"),
    ("Qualcomm Snapdragon X2 Elite Extreme", 2026, 228, 128, 80, "Qualcomm brief: 192-bit, 9523 MT/s, 228 GB/s, 128+ GB, 80 TOPS"),
    ("NVIDIA RTX Spark (N1X)",               2026, 273, 128, None, "press: 128 GB unified LPDDR5X, NVLink-C2C, 'a claimed 1 petaflop'; bandwidth assumed = GB10"),
    ("Apple M4 (MacBook Air)",               2024, 120, 32,  38, "Apple: 120GB/s; Neural Engine 38 TOPS"),
    ("Apple M4 Pro (Mac mini)",              2024, 273, 64,  38, "Apple: 273GB/s; the same 256-bit width as the widest copies"),
    ("Apple M5 Max",                         2026, 614, 128, None, "Apple: 614GB/s"),
]
print(f"{'chip':38} {'year':>4} {'GB/s':>5} {'max GB':>6} {'NPU TOPS':>8} {'9B ceiling':>10} {'27B ceiling':>11}")
for name, yr, bw, gb, tops, src in chips:
    c9 = f"{bw/4.47:10.0f}" if gb >= 8 else f"{'no fit':>10}"
    c27 = f"{bw/14.42:11.0f}" if gb >= 20 else f"{'no fit':>11}"
    print(f"{name:38} {yr:4d} {bw:5d} {gb:6d} {(str(tops) if tops else '—'):>8} {c9} {c27}")
print("\nTOPS is a compute figure for the NPU; decode divides bytes by GB/s and never sees it. Sort by the bandwidth column.")

# chip                                   year  GB/s max GB NPU TOPS 9B ceiling 27B ceiling
# Qualcomm Snapdragon X Elite            2024   135     64       45         30           9
# Qualcomm Snapdragon X2 Elite           2026   152    128       80         34          11
# Qualcomm Snapdragon X2 Elite Extreme   2026   228    128       80         51          16
# NVIDIA RTX Spark (N1X)                 2026   273    128        -         61          19
# Apple M4 (MacBook Air)                 2024   120     32       38         27           8
# Apple M4 Pro (Mac mini)                2024   273     64       38         61           19
# Apple M5 Max                           2026   614    128        -        137          43

External links

Exercise

Take the launch page of any AI PC and write down the first performance number it shows. Then find its memory bandwidth and maximum memory, compute the 9B ceiling, and write both numbers on your card side by side. Note which one the vendor led with and which one decides a token.
Hint
The first number is almost always TOPS. If the bandwidth is not on the page, width × rate ÷ 8 from the memory spec gives it; if the memory spec is not on the page either, the machine was not built with this workload in mind, and that is the finding.

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